Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

You will have:

  • B.Tech/M. Tech in CS/EE from a reputed institute.
  • Sound knowledge in data structures, graph algorithms and C/C++ programming on Windows/Unix.
  • Familiarity in digital logic design.
  • Familiarity with Verilog/VHDL RTL level designs, timing constraints, static timing analysis

Preferred Experience

  • 0-2 years of experience in designing, developing and maintaining large EDA software. 
  • Working knowledge of FPGA prototyping tools and flows is a plus.

Job Category : Engineering

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